The present invention relates to a power supply which is included in a display apparatus such as a liquid crystal display apparatus and used for supplying electric power for driving display pixels, and a display apparatus equipped with the power supply.
Referring to FIG. 4 which is an explanatory drawing of the present invention, the following description will discuss a liquid crystal display apparatus which is an example of a display apparatus.
On the side of segment electrodes of a liquid crystal panel 1, a segment driver 3 for driving segment electrodes X1-Xm is provided, while on the side of common electrodes, a common driver 2 for driving common electrodes Y1-Yn is provided. To the segment driver 3, a power supply circuit (power supply) 5 supplies driving electric powers V0, V2, V3, and V5. In contrast, to the common driver 2, the power supply circuit 5 supplies driving electric powers V0, V1, V4, and V5.
Various circuit arrangements have conventionally been proposed as the power supply circuit 5 which supplies the driving electric powers V0-V5. By the way, in the power supply circuit 5, a generation circuit for supplying voltages to the segment driver 3 is substantially identical with a generation circuit for supplying voltages to the common driver 2. Therefore the generation circuit for supplying a voltage for the segment driver 3 is taken as an example here, for the sake of simplicity.
For instance, a power supply circuit 35, which is illustrated in FIG. 7, outputs driving electric powers V0, V2, V3, and V5 by voltage-dividing using resistances. In this power supply circuit 35, three bleeder resistances R101, R102, and R103 divide the voltage between an electric power (VEE) and a ground (GND) so as to generate two intermediate voltages, and these two are outputted as driving electric powers V2 and V3.
In contrast, as illustrated in FIG. 8, a power supply circuit 36 is arranged such that lines, which are used for obtaining the driving electric powers V2 and V3 by voltage-dividing using resistances in the power supply circuit 35 in FIG. 7, are connected with operational amplifiers OP1 and OP2, for dropping the impedance of an output stage. This power supply circuit 36 makes it possible to regulate the driving electric powers V2 and V3 generated by way of voltage-dividing, by carrying out impedance conversion in the operational amplifiers OP1 and OP2.
In the power supply circuits 35 and 36, the values of the bleeder resistances R101 through R103 are preferably small, to reduce the voltage fluctuation and to regulate the voltages of the driving electric powers V0, V2, V3, and V5, even if pixels of the liquid crystal panel 1 which is a capacity load are charged or discharged. However, when the values of the bleeder resistances R101 through R103 are small, the power consumption in the power supply circuits 35 and 36 is high.
Moreover, when the operational amplifiers OP1 and OP2 in the power supply circuit 36 obtain enough electric power for liquid crystal displaying, constant currents in the operational amplifiers are high to a certain extent, and this obstructs the reduction of the power consumption. That is, in each of the operational amplifiers OP1 and OP2, constant current sources are mainly provided in (i) a differential pair section in the input stage and (ii) the output stage, and especially the constant current source in the output stage, which is provided as a load circuit, cannot follow the voltage fluctuation if the value of the constant current is low.
To solve the above-identified problem, Japanese Laid-Open Patent Application No. 55-146487/1980 (Tokukaisho 55-146487; published on Nov. 14, 1980) discloses a power supply circuit which is basically arranged similar to the aforementioned power supply circuit 35 but the driving electric powers V0, V2, V3, and V5 can be regulated despite the values of the bleeder resistances are risen in order to reduce the power consumption.
As FIG. 9 illustrates, a high voltage side is grounded in a power supply circuit 37 disclosed by the publication above, and thus driving electric powers V0, xe2x88x92V2, xe2x88x92V3, and xe2x88x92V5 are acquired. The power supply circuit 37 is arranged so that output voltages which are outputted as the driving electric powers xe2x88x92V2 and xe2x88x92V3 are generated by bleeder resistances (hereinafter, will be simply referred to as resistances) having high resistance values, and fluctuations surpassing acceptable voltage values of the respective driving electric powers xe2x88x92V2 and xe2x88x92V3 are detected so that the fluctuations are restrained by MOS transistors MQ11 through MQ14. Incidentally, DN is an electric power node and SN is a grounding node in FIG. 9.
In the power supply circuit 37, series resistances R101 through R103 are resistance voltage-dividing circuits, in which a voltage xe2x88x92V5 of an electric power E is divided in three so that intermediate voltages which are to be the driving electric powers xe2x88x92V2 and xe2x88x92V3 are obtained. Then with reference to the divided voltages xe2x88x92V2 and xe2x88x92V3 which are intermediate voltages obtained by voltage-dividing using resistances, reference voltages xe2x88x92VH2, xe2x88x92VL2, xe2x88x92VH3, and xe2x88x92VL3 for setting respective acceptable ranges xcex94V of the voltage fluctuations are generated by a voltage dividing circuit constituted by series resistances R104-R108.
Moreover, a voltage comparator circuit (hereinafter, will be simply referred to as comparator) CMP1, whose inverting input terminal receives the reference voltage xe2x88x92VH2 while non-inverting input terminal receives the divided voltage xe2x88x92V2, and an nMOS transistor MQ12, which is connected between a divided voltage output point and the voltage xe2x88x92V5 of the electric power E and controlled by the output of the comparator CMP1, are provided, so that when the output voltage of a line through which the divided voltage xe2x88x92V2 runs varies so as to surpass the reference voltage xe2x88x92VH2 in the positive direction (towards the ground voltage), the nMOS transistor MQ12 is turned on in order to restrain the output fluctuation surpassing the acceptable range xcex94V in the positive direction.
Meanwhile, (i) a comparator CMP2 whose non-inverting input terminal receives the reference voltage xe2x88x92VL2 while inverting input terminal receives the divided voltage xe2x88x92V2 and (ii) a pMOS transistor MQ11, which is connected between the divided voltage output point and the ground voltage V0 and controlled by the output of the comparator CMP2, are provided, so that when the output voltage of a line through which the divided voltage xe2x88x92V2 runs varies so as to surpass the reference voltage xe2x88x92VL2 in the negative direction (towards the voltage xe2x88x92V5), the pMOS transistor MQ11 is turned on in order to restrain the output fluctuation surpassing the acceptable range xcex94V in the negative direction.
Likewise, the fluctuation of the output voltage xe2x88x92V3, which surpasses the acceptable range xcex94V, is restrained. That is to say, a comparator CMP3, whose inverting input terminal receives the reference voltage xe2x88x92VH3 while non-inverting input terminal receives the divided voltage xe2x88x92V3, and an nMOS transistor MQ14, which is connected between the divided voltage output point and the voltage xe2x88x92V5 of the electric power E and controlled by the output of the comparator CMP3, are provided, so that when the output voltage of a line through which the divided voltage xe2x88x92V3 runs varies so as to surpass the reference voltage xe2x88x92VH3 in the positive direction (towards the ground voltage), the nMOS transistor MQ14 is turned on in order to restrain the output fluctuation surpassing the acceptable range xcex94V in the positive direction.
In the meantime, (i) a comparator CMP4, whose inverting input terminal receives the reference voltage xe2x88x92VL3 while non-inverting input terminal receives the divided voltage xe2x88x92V3, and (ii) a pMOS transistor MQ13, connected between the divided voltage output point and the ground voltage V0 and controlled by the output of the comparator CMP4, are provided, so that when the output voltage of a line through which the divided voltage xe2x88x92V3 runs varies so as to surpass the reference voltage xe2x88x92VL3 in the negative direction (towards the voltage xe2x88x92V5), the pMOS transistor MQ13 is turned on in order to restrain the output fluctuation surpassing the acceptable range xcex94V in the negative direction.
On this account, the voltage fluctuations of the output voltages corresponding to the respective divided voltages xe2x88x92V2 and xe2x88x92V3 which are to be the driving electric powers xe2x88x92V2 and xe2x88x92V3 are restrained so as to fall within the acceptable ranges xcex94V which are determined by the voltage drop caused by the resistances R105 and R107.
This power supply circuit 37 is arranged so that the power consumption can be restrained by specifying the values of the resistances R101-R103 and R-104-R108 high, and since the MOS transistors MQ11-MQ14, which are activated only when the voltage fluctuation surpasses the acceptable ranges xcex94V and have high current driving ability (i.e. capable of feeding a large amount of current), are provided in the output stages, the driving abilities of the output stages of the comparators CMP1-CMP4 are not necessarily high. Thus it is possible to reduce the currents supplied from the constant current sources provided in the comparators CMP1-CMP4 so that the power consumption of the power supply circuit 37 can be significantly reduced.
Furthermore, each of the MOS transistors MQ11-MQ14 has an offset voltage thanks to the acceptable range xcex94V so that only one of the transistors MQ11-MQ14 is turned on at a time, and thus a through current (a current which runs due to the shorting of two power supply lines paring up with each other) is not generated.
As a result, the power supply circuit 37 arranged as above can be a power supply circuit of a display apparatus, which consumes a small amount of electricity and produces consistent output voltages.
Generally speaking, a load-carrying capacity of each pixel and a parasitic capacitance of each electrode line are large in a large-size liquid crystal panel, and hence the power supply circuit has to have high driving ability, in order to precipitously carry out charging or discharging the members above. Also, to obtain a high-quality image, the power supply circuit is required to have a driving electric power with small voltage fluctuation, to promptly respond to the fluctuation, and to consume a small amount of electricity.
So, in the power supply circuit 37 (FIG. 9), the divided voltages xe2x88x92V2 and xe2x88x92V3, which are to be the driving electric powers xe2x88x92V2 and xe2x88x92V3, are speedily brought back to the respective acceptable ranges xcex94V thanks to the MOS transistors MQ11-MQ14 which have high driving ability. However, once the divided voltages xe2x88x92V2 and xe2x88x92V3 are brought back to the respective acceptable ranges xcex94V, the resistances R101-R103 make these voltages converge to respective targeted voltage values. By the way, the targeted values are voltage values outputted between the resistances connected in series. Thus, in the circuit arrangement of the power supply circuit 37, the convergent to the targeted voltage values takes much time when the resistances R101-R103 have high resistance values.
As a result, in the power supply circuit 37, when the values of resistances R101-R103 and the resistances R104-R108, each group of the resistances constituting a resistance voltage-dividing circuit, are arranged so as to be high in order to further reduce the power consumption, it takes long time to regulate the output voltages corresponding to the divided voltages xe2x88x92V2 and xe2x88x92V3 at the respective targeted values (i.e. it takes long time until the voltage values converge to the respective targeted values within the acceptable ranges xcex94V). On this account, the power supply circuit 37 will not be able to comply with further enlargement of the screen and improvement of image quality of the liquid crystal display, due to the occurrence of the degradation of the image quality.
Moreover, the power supply circuit 37 includes two groups of resistances, namely the resistances R101-R103 and the resistances R104-R108, as the resistance voltage-dividing circuits, so that the power consumption in this arrangement is inevitably higher than the power consumption of the arrangement in which only one group of resistances are adopted as the resistance voltage-dividing circuit.
Furthermore, since the power supply circuit 37 determines the voltage-dividing ratio by the resistances R101-R103 provided in the output stage, it is necessary to keep the voltage-dividing ratio when the resistance values of the resistances R101-R103 are changed. Thus, the size of the respective circuits is increased when a programmable modification of the resistance values using an internal resistor is carried out.
The present invention was done to solve the above-identified problems, so as to aim at providing a power supply: being able to keep up with further increase of the display screen without the degradation of the quality of display images, as well as further improvement of the quality of display images; being capable of steadily supplying driving electric powers by an output voltage with a small fluctuation and rapidly restoring the regulated state when the output voltage fluctuates, despite consuming a small amount of electricity; and being capable of adopting programmable modification of the resistance values using an internal resistor without the increase of the size of the power supply. Furthermore, the present invention aims at providing a display apparatus including the above-mentioned power supply.
To solve the problems above, the power supply in accordance with the present invention includes: a resistance voltage-dividing circuit for generating an intermediate voltage, whose targeted voltage value is specified, from a supplied voltage; at least one voltage follower circuit including (i) an N-type transistor for causing a current flow into the at least one voltage follower circuit from an outside when the intermediate voltage is higher than the targeted voltage value and (ii) a P-type transistor for outputting a current to the outside when the intermediate voltage is lower than the targeted voltage value, a fluctuation acceptance range of the intermediate voltage with respect to the targeted voltage value being specified so as to be equivalent to a difference between an operation-starting voltage of the N-type transistor and an operation-starting voltage of the P-type transistor; and a resistance for regulating the intermediate voltage at a value approximately equal to the targeted voltage value, by activating either one of the P-type transistor or the N-type transistor so as to vary the intermediate voltage.
According to this arrangement, when the intermediate voltage significantly fluctuates so as to surpass the target voltage value, either one of the P-type transistor and the N-type transistor of the voltage follower circuit, the transistor being capable of bringing the intermediate voltage back to the targeted voltage value, operates so that the deviated intermediate voltage is rapidly brought back to the targeted voltage value. Here, in the voltage follower circuit, a fluctuation acceptance range of the intermediate voltage with respect to the targeted voltage value is specified so as to be equivalent to a difference between an operation-starting voltage of the N-type transistor and an operation-starting voltage of the P-type transistor.
On this account, the intermediate voltage is kept within the fluctuation acceptable range without being significantly deviated from the targeted voltage value. That is to say, the intermediate voltage is regulated so as to be, for instance, within the fluctuation acceptable range having its center at the targeted voltage value (between the maximum and minimum voltage values). However, in the arrangement above, the intermediate voltage is hardly kept at a fixed value within the fluctuation acceptable range so as to be easily fluctuate. By the way, the reasons, etc. of this will be specifically described in Description of the Embodiments.
Thus, the power supply is provided with a resistance, for eliminating the above-identified fluctuation of the intermediate voltage. This resistance is arranged such that the P-type transistor or the N-type transistor is activated so that a current is supplied to the outside or pulled in from the outside, and hence the intermediate voltage outputted from the output stage is varied so as to be approximately equal to the targeted voltage value. On this account, Without the fluctuation within the fluctuation acceptable range around the targeted voltage value, the intermediate voltage is forcibly varied so as to be approximately equal to the targeted voltage value, and consequently the intermediate voltage is regulated and stabilized.
In this manner, the power supply is arranged so that, when the intermediate voltage fluctuates so as to surpass the fluctuation acceptable range, either the P-type transistor or the N-type transistor operates so that the intermediate voltage is rapidly brought back to the fluctuation acceptable range. Moreover, when the intermediate voltage fluctuates within the fluctuation acceptable range, thanks to the operation of either the P-type transistor or the N-type transistor, the intermediate voltage value is forcibly varied so as to be approximately equal to the targeted voltage value, and consequently regulated. On this account, the intermediate voltage is regulated at a voltage value approximately equal to the targeted voltage value, without the fluctuation within the fluctuation acceptable range.
Therefore, in spite of the low-power-consumption, the power supply can steadily supply driving electric powers by an output voltage with a small fluctuation and rapidly restoring the regulated state when the output voltage fluctuates, and hence the power supply can keep up with further increase of the display screen without the degradation of the quality of display images as well as further improvement of the quality of display images.
Furthermore, according to the arrangement above, since the fluctuation of the output voltage can be restrained so as to be regulated without providing a bleeder resistance in the output stage, it is possible to realize further reduction of the power consumption. Moreover, since the voltage-dividing ratio is not determined by the bleeder resistance in the output stage, the size of the circuit does not increase even if the programmable modification of the resistance values using an internal resistor is carried out.
Moreover, to solve the problems above, the display apparatus in accordance with the present invention, including a display panel, a drive unit for driving the display panel, and a power supply for supplying driving electric power, which is for driving the display panel, to the drive unit, further includes the aforementioned power supply in accordance with the present invention.
As described above, the power supply in accordance with the present invention is arranged so as to: be able to keep up with further increase of the display screen without the degradation of the quality of display images, as well as further improvement of the quality of display images; be capable of steadily supplying driving electric powers by an output voltage with a small fluctuation and rapidly restoring the regulated state when the output voltage fluctuates, despite consuming a small amount of electricity; and be capable of adopting programmable modification of the resistance values using an internal resistor without the increase of the size of the power supply.
Thus, thanks to the arrangement as above, using this power supply enables to realize a display apparatus with a large screen, good display quality, and low-power-consumption.